Schematics of the Powerboard Tyche Desktop version Completed! Soon starting the PCB design

Posted on by Communications Team

We now have the complete electronic source design for our new desktop design in our hands!

This week, ACube Systems and some volunteers from our association will review the design. We expect the manufacturer to start setting up the PCB layout for the new Powerboard Tyche Desktop on October 20th. This is part of our strategy to focus on creating a stable, functional desktop version of the core computing platform by the end of 2025.

The PCB design phase (Phase 2) will begin shortly after the schematics and Bill of Materials (BOM) are sent to the manufacturer. We anticipate that this step will allow the manufacturer to provide us with an estimate of the cost and timeline for the PCB layout design. This cost and timing estimate will then be shared with the community “just in time.”

Technical Components and NXP Review

We have verified that the availability of SATA2/3 controllers is poor, and the chip Lattice Silicon Image SiI3132 chip that we selected is no exception. We decided to include it in our desktop board to ensure backward compatibility with SATA devices, such as DVD and HDD.

We do not use the on-chip T2080 SATA2 controller because we prefer to use the T2080’s three x4 PCIe Gen3 configuration to optimize the speed of video cards and storage controllers. This configuration cannot coexist with the on-chip SATA2. In any case, the best performance is possible thanks to our M2 motherboard interfaces.

In our board design, we have an SPI connection for an external LCD, which can be used as a secondary screen or for debugging and diagnostics. It is also useful when setting up u-boot and when no video card is connected to the board.

Our board design includes GPIO connectors that can be used to connect other devices that don’t use USB, SPI, or PCIe buses.

Our desktop design is derived from our old notebook design and the original NXP T2080 RDB (Release F) design. We are integrating many components specified in the reference board, including critical monitoring hardware.

This includes the OnSemi ADT7481ARMZ thermal monitor, which has been upgraded to the OnSemi NCT72. The ADT7481 is used as the thermal monitor or temperature sensor on the original NXP T2080 reference design board. On that board, the ADT7481 (designated U34) is usually connected via the I2C_1 bus with the address 0x40. The T2080 processor itself contains a temperature diode designed to be used with system temperature monitoring devices, such as the Analog Devices ADT7461A. This similar part is mentioned in the documentation for the T1042 chip, which highlights the standard use of such monitoring.

Designers have changed other components from the original T2080 RDB design and our notebook design due to the availability of new compatible models, such as the N25Q512A13 FLASH SPI, which is substituted for the EvKit Micron MT25QL512A due to its limited availability.

Due to the changes in components, we will need to modify the VHDL code of the CPLD chip when we have the prototypes in our hands. Therefore, we must take into account the additional cost of this task.

To ensure full compliance and open-source publication readiness,

  1. The designer will fill out the NXP review questionnaire [draft post 2025-10-12] simultaneously.
  2. The questionnaire and the Cadence schematic source will then be sent to NXP.
  3. The main goal is to receive a full or partial agreement to publish the parts of our design derived from the original NXP T2080 RDB (Release F) as open hardware.

We anticipate a robust boot-up because the components and firmware are similar to those of the stable T2080 RDB. The specific CPLD is programmed using the original CPLD source code of the T2080 RDB. Once NXP grants the necessary agreement, we plan to publish the source schematics and evaluate the use of a recent CERN Open Hardware License version.

Upcoming Project Phases

The next anticipated milestones, pending finalization of cost estimation:

  • Phase 2: PCB design. (tentatively scheduled two months after the completion of the schematics).
  • Phase 3: Prototype production (tentatively scheduled one month after PCB design).
  • Phase 4: Prototype testing (tentatively scheduled one month after prototype production).

We continue to rely on the community’s support. Recurring donations are dedicated to the campaign aimed at recovering costs already incurred for notebook testing and CPLD firmware fixing.

We are searching volunteers to test Debian PPC64 and fix packages

Finally, we need more volunteers to support the necessary software efforts, including Debian PPC64 testing, as we cannot ask for additional donations for this purpose.

Below is an updated list of specs for the desktop board being designed.

Form Facttor: Micro ATX
CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
    4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
RAM: 2 x DDR3 Slots
VIDEO
    PCIE3 x16 VIDEO Card 1
    PCIE2 x16 VIDEO Card 2
AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks (3x2)
USB:  2 USB 3.0 ports
      2 USB 2.0 ports
      2 USB 3.0 ports internal for FRONT
STORAGE:
    2 NVM Express (NVMe)
    2 x SATA2
    1 x SDHC card reader
NETWORK:
    2 x Gigabit ethernet RJ-45 connector
38.17% Raised
€2,061.56 donated of €5,400.00 goal
21 Donors
3 Days Left

New Powerboard Tyche Desktop design Faster then Ever!

Posted on by Communications Team

To complete the schematics design, the designer will need around another two weeks.
From the beginning of August we already have in our hands a large part of the new design (Desktop version of Powerboard Tyche motherboard). We have started a fast review thanks to a few members of our association that were able to check the schematics. As usual in Italy, during August companies close for at least two weeks for vacations, so the designing is slowing down. For that reason, the PCB design will start after the middle of September.

We are proceeding faster than ever. We started the “Powerboard Tyche Desktop Electrical Schematics Design” donation campaign on 14th July, and the design itself started at the beginning of July. So after 1 month we already had a good part of the schematic done! Comparing that time with around 12 months that took the Notebook schematics design, now we are proceeding more than 4 times faster!!!

Thanks to the previous work done, our previous design and experience doing Powerboard Tyche Notebook designs and prototypes, the designer can realize the Desktop Design faster, integrating the NXP T2080 RDB design (revision F – year 2023). That design is possible thanks to the 5400 euro of the dedicated Donation Campaign. The old donation campaign to design the Schematics of Powerboard Tyche Notebook was 12600 euro, so now we are spending less than half.

So every past effort and past donations for the Notebook version campaigns have been invaluable and permit us to speed up time and limit the cost to design the current Desktop version.

38.17% Raised
€2,061.56 donated of €5,400.00 goal
21 Donors
3 Days Left

We remain absolutely committed to making an Open-Hardware Notebook-based PowerPC machine a reality. The desktop version will be the right step to allow more people, spending less money, to soon own, enjoy, and test software on this Desktop version. With a few changes and reintegrating the battery part of our previous Notebook, it will give rise to the Notebook version!

You can check our timeline from 2015 to 2025 and milestones of the project during the years.

NXP will review our Powerboard Tyche Desktop Electrical Schematics Design before we can publish it (completely or partially), as we have received from them Cadence source of the NXP T2080RDB (revision F – year 2023) that the designer has modified and partially integrated with our previous Notebook design (you can see our architectural study published even in the last post). We thank NXP for having provided us this source (revision F) that actually is not published. For that reason we need to have their agreement to publish, with an Open Hardware license, the parts that we take from their source. The Notebook version is published with a CERN Open Hardware license 1.2 version.

Hardware designers in NXP, as our old designer and the new one, use Cadence to design schematics, so that forces us to have the source in Cadence. We are not hardware designers.
The PCB design of the Notebook board was done in Mentor Expedition and the Desktop Design will be done in Mentor Pads.

As we did with our Powerboard Tyche Notebook design, we will convert the Cadence and Mentor Pads sources to Altium and then to KiCad, hoping that the conversion to KiCad has been further improved and allows nothing to be lost.

For us, it is of fundamental importance that our board is Open Hardware (we will certify it as Open Hardware with OSHWA when it will be completely functional) and the prototypes are realized thanks to your support and donations.

OSHWA Certification

The process required to achieve a fully compliant Open Hardware motherboard was carefully analyzed by students of the Law and Policy Clinic of New York University School of Law (in 2019). Thanks to their work, we clearly understood the practical implications of the requirements for the OSHWA Open Hardware certification, and we cross-checked our approach and adopted solutions with OSHWA personnel. An important part of being considered Open Hardware compliant (OSHWA Open Hardware certification) requires that everything that is under our control and used to produce our motherboard should be publicly disclosed, such as schematics, PCB, Gerber-files and all their accompanying information. As a consequence, most of the datasheets of the chips used in our schematics are freely downloadable, as well as the schematics and the PCB design. In case some of the chip vendors ask us to remove technical details that we were not supposed to disclose, we will comply with their requests by removing the published material, but that will not impact our compliance with OSHWA Open Hardware certification, because we can demonstrate that we strived to be as open as possible.

What’s more, we thank NXP for reviewing our design. We had to fill a deep questionnaire that permits them to go deeper into the review. This is an added value that NXP gives to our board: they use their time and resources for us, and we are grateful for that.
In the worst case, they will ask us to mask some parts of the source that are copied from their design. That is the reason why, before publishing the schematics sources, we need to complete it and wait for their review. In this way, we have sped up the design process; we are going on with our design phases without waiting for NXP review. The review only delays the moment in which we start publishing the open source designs.

We are searching for volunteers that would like to improve our Open Hardware license and evaluate if it is better to use a newer CERN Open Hardware version than continuing with version 1.2.

What happens when the schematics design will be completed?
In the middle of September we should have in our hands the schematics design and the BOM that we will forward to the company that will make for us the PCB design and prototype production.
This manufacturer company is already booked and ready for the middle of September to carry out these activities for us. The first feedback that this company will give to us will be the cost estimation to design the PCB and to produce our Desktop prototypes, so at the same moment we will be able to inform everyone about the costs of each phase (PCB, prototypes).

Then they will start the PCB design (phase 2) and order the electronic components needed for the prototype production (phase 3).
After the prototype production, hardware and firmware testing will start (phase 4). With the CPLD itself, starting from the original CPLD source code of T2080 RDB, our Powerboard Tyche Desktop CPLD will be programmed.
As the components and firmware to boot up the board are the same as the T2080 RDB, we can count on a robust boot up.
If more work is needed to improve the CPLD code, it will be done thanks to the same firmware engineer that helped us fix the CPLD firmware of our Notebook prototype, and in that case we will evaluate the cost (phase 4 bis).

Yes, it’s possible to reach the goal to have a working Powerboard Tyche Desktop before the end of 2025, but is needed an extraordinary effort from donors because we depend on donations to cover all the steps that are coming : Schematics Design, PCB Design, Prototype Production and Tests.

38.17% Raised
€2,061.56 donated of €5,400.00 goal
21 Donors
3 Days Left

Desktop Electrical Schematics Ready! in August.25

Posted on by Communications Team

We are very happy to inform you that the Schematics Design of our new Powerboard Tyche Desktop is running fast thanks to the new Designer and to the NXP Devkit source design plus our Powerboard Tyche Notebook design. Designer took from the NXP Devkit design ( 2023 version) everything is related to the boot process and many parts from our Notebook design, except what is not needed for the Desktop version, like the Battery part.

You can check all the details regarding what we took from Devkit design and what we took from our Powerboard Tyche Notebook design.

At the end of July, we will provide the schematic design and the BOM to the factory, which will then begin the PCB design based on the schematics. Therefore, by the beginning of August (before the factory’s holiday closure), we will know the cost for the PCB design and prototype production. New donation campaigns will then start for PCB design and prototype production.

Today, July 14th, 2025, we’ve officially launched the donation campaign for the schematics. Before the end of July, we’ll make the down payment for the schematics design. We already have funds collected from the previous donation campaign for the CE certification (of the Powerboard Tyche Notebook), so we can advance money from that fund. However, it’s crucial to boost this new campaign and encourage everyone to donate so we can use fresh funds specifically for the schematics design.

SPECS

  • Form Facttor: Micro ATX
  • CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
    • 4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
  • RAM: 2 x DDR3 Slots
  • VIDEO
    • PCIE3 x16 VIDEO Card 1
    • PCIE2 x4 VIDEO Card 2
  • AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks
  • USB: 3.0 and 2.0 ports
  • STORAGE:
  • NETWORK:
    • 2 x Gigabit ethernet RJ-45 connector
38.17% Raised
€2,061.56 donated of €5,400.00 goal
21 Donors
3 Days Left

Yes, it’s possible to reach the goal to have a working Powerboard Tyche Desktop before the end of 2025, but is needed an extraordinary effort from donors because we depend on donations to cover all the steps that are coming : Schematics Design, PCB Design, Prototype Production and Tests.

Starting from today (July 14th 2025) you can make your donation, thanks!

Milestones

Phase 1: Actual Campaign Schematics Design : goal 30.07.2025

Phase 2: PCB Design : goal 30.09.2025 [depending on donations collected]

Phase 3: Prototypes Production: goal  30.10.2025 [depending on donations collected]

Phase 4: Prototypes Tests. : goal  30.11.2025 [depending on donations collected]

The milestone phases depend from your donation. Thanks!

We remain absolutely committed to making an Open-Hardware Notebook-based PowerPC machine a reality.

As we have already published on our past post we have changed the tactic, focusing on a desktop board first allows us to concentrate on getting the core computing platform stable and functional, tackling the complexities of a laptop form factor (like power management, screen integration, etc.) in a later stage if needed. This is a pragmatic step to ensure we achieve a tangible outcome by our 2025 target. What’s more the Powerboard Tyche Desktop version will be more cheaper than the Notebook version!

We value the experience of making our Open Hardware Powerboard Tyche based on PowerPC from scratch; this is possible thanks to the support of all donors and supporters, and the time and creativity of the activists who have been involved in this project over the years.

Image by Free Fun Art from Pixabay

We ask you to share every-ware this call for support a strong flow of donations to cross the finish line of all donation campaigns to arrive by 2025 with produced, tested and functioning prototypes!

Forging the Future of Open Source Lab that provide us Power Architecture VM

Posted on by Roberto Innocenti

As we have published many times in our posts we use 2 Power9 VM for free thanks to the Open Source Lab at Oregon Stage University.

At 30th April 2025 the OSL published

critical and time-sensitive situation facing the Open Source Lab (OSL). Over the past several years, we have been operating at a deficit due to a decline in corporate donations. While the Oregon State College of Engineering (CoE) has generously filled this gap, recent changes in university funding makes our current funding model no longer sustainable. As a result, our current funding model is no longer sustainable.

On 9th May 2025 published

Following our OSL Future post, the community response has been incredible! Thanks to your amazing support, our team is funded for the next year. This is a huge relief and lets us focus on building a truly self-sustaining OSL.

Now they need support to build a truly self-sustaining OSL, they serve and help many of Open Source projects like our, so we publish their call.

https://osuosl.org/blog/osl-future-update

Strategic Change: By 2025, let’s do whatever It Takes to achieve at Least a desktop version!

Posted on by Communications Team

Hello everyone, we know it’s been quite some time since our last update on November 21, 2024.

We really appreciate your patience! Despite the silence on our end, we’ve seen that our incredible community – both old friends and new supporters – have continued to donate continuously. An infinite thanks to all of you, our amazing current, past, and future donors! Your unwavering support truly fuels our efforts and keeps the dream alive.

Image by Tú Anh from Pixabay

Short story

As we shared in our last post, the work with the previous designer hit a significant hurdle: we just couldn’t get the board to reach the crucial boot stage.

This led us on a search for a new designer, someone with specific skills and experience with PowerPC architecture. We were really pleased to find a talented new designer who was available from the beginning of 2025, who can even rely on an additional person who is an expert in firmware programming. Following our plan, we used January and February to make the big move, getting all the equipment transferred over to this new designer’s team.

We held off on publishing updates because, honestly, we were waiting for that breakthrough moment – the good news we could finally share with all of you. As things were showing quite promising (e.g. improved CPU signals outputs), we had high hopes that this new collaboration would quickly move us past the booting issues. In parallel, we also tried improving U-Boot and led an additional T2080RDB, the development board that was kindly provided by NXP, to one of our collaborators, but due to personal health problems, he can no longer contribute to the project.

Our work with the new designer has been focused on rigorous testing. On April 9th, we saw that the board’s behavior was frustratingly similar to the devkit – it still wasn’t booting. This prompted a dedicated session on April 14th for one last intensive attempt to find the root cause. As part of this deep dive, we de-soldered the Marvell chip, which is the SATA3 controller.

Marvell 88SE9235A1-NAA2C000 Sata 3 chip removal to test Powerboard Tyche

Removing this component was actually something we had already planned to do for the upcoming prototype version as we streamline the design. To help isolate the issue even further, we also de-soldered the Pericom chip.

removal Pericom 6-port, 12-lane, PCIe 2.0 Packet Switch PI7C9X2G612GP

The overall outcome? Despite taking these significant steps, the board still did not boot. It exhibited exactly the same behavior. We were, frankly, quite upset and left without words.

It’s incredibly challenging when you put in the effort, try to simplify things, and the core problem persists. So far, we have spent around 6000 Euros with the newly hired hardware designer, and even if things have improved, showing the expected NXP documented behaviors of the NXP reference development board, after two years with the prototype motherboards in our hands, we still are not able to boot it.

Read more: Strategic Change: By 2025, let’s do whatever It Takes to achieve at Least a desktop version!
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